Silicon devices radiation hardening can be faced from two points of view:
- Radiation Hardening by Process (RHBP) which takes into account the base technology to be used for the development of silicon base integrated circuits.
- Radiation Hardening by Design (RHBD) which applies dedicated design methodologies for the same purpose.
Starting from a standard and consolidated silicon process, a reasonable resistance to radiation can be achieved focusing on RHBD.
In SkyFlash project a standard CMOS 180 nm process technology, actually used for non-space applications, is chosen as the building block for the development of a rad-hard methodology focusing only on RHBD.
RHBD on CMOS may count on the following advantages:
- maturity of the process and very high repeatability;
- low cost;
- availability from many silicon foundries;
- MPW (Multi Project Wafer) approach (low cost and quick prototyping, low volume productions);
- RHBD technical solutions are portable.
RHBD can be divided into three different approaches depending on the level of complexity with which silicon device is considered.
- RHBD-AL: Radiation Hardening By Design at Architecture Level.
- RHBD-CL: Radiation Hardening By Design at Circuit Level.
- RHBD-LL: Radiation Hardening By Design at Layout Level.
The very basic purpose of SkyFlash project is to organise all these methods (many of them actually are used as practice and not as method) and to obtain a good balance.
A semiconductor memory must be considered as an ensemble of some primary macro blocks: these are the memory array (which is the core where bits are stored), row decoders, column decoders (in order to select the single bit to be read), sensing blocks (devoted to reading memory cells), programming and erasing blocks and so on.
The entire architecture must be considered taking in mind that heavy ions can strike at any moment, in a random way, every part of the device. If the impact involves a single memory cell we may have an error but if the same impact involves, for example, a row decoder we may have more errors along a word line (at least 8 if we consider the byte) thus leading to a proliferation of errors. RHBD-AL methodologies so suggest to replicate row decoders to reduce on one side the probability of errors and on the other the entity. So, architecturally speaking, the array can be divided in more sub-arrays each one independent to the others and each one complete of what it needs to be independent (autonomous row and column decoding). This is an example of RHBD from architecture point of view actually used for rad-hard SRAMs that could be ported to non volatile memory architectures.
RHBD-CL is the typical domain of analog semiconductor designers.
In this domain the single block or circuit such as operational amplifiers, input/output buffers, differential stages, multiplexers, NANDs, NORs or even the single inverter are taken into account having clearly in mind that an high-energy particle may collide with the circuit. At this level many precautions must be taken. First of all avoid feedback loops (in particular positive ones) or, if needed, controlled by alternative topologies.
A good example could be the latch as the core of a Flip-Flop or as the core of a SRAM cell. As well known in literature two inverters are connected the output of the first to the input of the other thus forming a positive feedback and leading to two different stable states which can be reached through other circuits stimulating in the right way this ensemble. Nevertheless a high energy particle can collide with the latch and, if enough energy is released, it may change one stable state with the other acting just like a stimulating circuit. To avoid this problem many solutions can be used such as the connection of a capacitor in parallel to the feedback loop (Miller Capacitor) in order to enhance stability of each state, or a resistor in the feedback path thus reducing the gain of the feedback loop so giving time to the inverter pairs to release the extra-energy provided by the particle.
RHBD-LL is the domain of layout designers. Following the architecture floorplanned and using libraries of elementary blocks (Rad Hard Libraries) the final chip layout is ensembled drawing every level of metal, polysilicon and defining active areas of transistors.
This domain is very tied to semiconductor physics and radiation effects must be considered either in short time terms (SEE, Single Event Effect) and long time terms (TID, Total Ionizing Dose). One of the well know degradation effects is the decrease of threshold voltage in n-channel MOS transistors due to silicon dioxide impurity; some traps can in fact retain charges (holes) and if these traps area sufficiently close to transistor channel they can vary the threshold of the transistor thus leading to a very elementary block having a behaviour changing in time.
The solution could be the physical design of a transistor not presenting edges in the direction of thick oxide: this is called EdgeLess Transistor (ELT) or Annular Transistor or Ring Transistor (due to its typical shape). ELTs are very robust to total dose effects but, unlike traditional stacked transistors, they occupy large area, in particular when minimum lithography is required. ELTs represent a typical RHBD-LL solution.